Ausws

Counselling Code

1121

Admission

Enquiry

044 - 27600731, 95669-39115

svis_tech@yahoo.com

Ausws

Counselling Code

1121

044 - 27600731, 95669-39115

info@svist.edu.in

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M.E – VLSI Design

PO'sPEO'sPSOSVLSI Design Laboratory-IVLSI Design Laboratory-IISoftware AvailableFaculty

PROGRAM OUTCOMES (POs)

Engineering Graduates will be able to:

  • Engineering knowledge: Apply the knowledge of mathematics, science, engineering fundamentals, and an engineering specialization to the solution of complex engineering problems.
  • Problem analysis: Identify, formulate, review research literature, and analyze complex engineering problems reaching substantiated
    Conclusions using first principles of mathematics, natural sciences, and engineering sciences.
  • Design/development of solutions: Design solutions for complex engineering problems and design system components or processes that meet the specified needs with appropriate consideration for the public health and safety, and the cultural, societal, and environmental Considerations.
  • Conduct investigations of complex problems: Use research based knowledge and research methods including design of experiments, analysis and interpretation of data, and synthesis of the information to provide valid conclusions.
  • Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern engineering and IT tools including prediction and modeling to complex engineering activities with an understanding of the limitations.
  • The engineer and society: Apply reasoning informed by the contextual knowledge to assess societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to the professional engineering practice.
  • Environment and sustainability: Understand the impact of the professional engineering solutions in societal and environmental contexts, and demonstrate the knowledge of, and need for sustainable development.
  • Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms of the engineering practice.
  • Individual and team work: Function effectively as an individual, and as a member or leader in diverse teams, and in multidisciplinary settings.
  • Communication: Communicate effectively on complex engineering activities with the engineering community and with society at large, such as, being able to comprehend and write effective reports and design documentation, make effective presentations, and give and receive clear instructions.
  • Project management and finance: Demonstrate knowledge and understanding of the engineering and management principles and apply these to one’s own work, as a member and leader in a team, to manage projects and in multidisciplinary environments.
  • Life-long learning: Recognize the need for, and have the preparation and ability to engage in independent and life-long learning in the broadest context of technological change.
The Programme Educational Objectives (PEOs) are,

  • To equip the graduates to have an in-depth knowledge along with new technical ideas, to analyse and evaluate the potential engineering problems and to contribute to the research and development in the core areas by using modern engineering and IT tools.
  • To demonstrate self –management and teamwork in a collaborative and multidisciplinary arena
  • To inculcate good professional practices with a responsibility to contribute to sustainable development of society.
  • To have a zeal for improving technical competency by continuous and corrective learning.
The Programme Specific Objectives (PSOS) are,

  • To design and develop VLSI circuits to optimize power and area requirements, free from faults and dependencies by modeling, simulation and testing.
  • To develop VLSI systems by learning advanced algorithms, architectures and software –hardware co –design.
  • To communicate engineering concepts effectively by exhibiting high standards of technical presentations and scientific documentations.
EXPERIMENTS:

  • Understanding Synthesis principles. Back annotation.
  • Test vector generation and timing analysis of sequential and combinational logic design realized using HDL languages.
  • FPGA real time programming and I/O interfacing.
  • Interfacing with Memory modules in FPGA Boards.
  • Verification of design functionality implemented in FPGA by capturing the signal in DSO.
  • Real time application development.
  • Design Entry Using VHDL or Verilog examples for Digital circuit descriptions using HDL languages sequential, concurrent statements and structural description.
EXPERIMENTS:

  • To synthesize and understand the Boolean optimization in synthesis. Static timing analyses procedures and constraints.
  • Critical path considerations.
  • Scan chain insertion, Floor planning, Routing and Placement procedures.
  • Power planning, Layout generation, LVS and back annotation, Total power estimate.
  • Analog circuit simulation.
  • Simulation of logic gates, Current mirrors, Current sources,
  • Differential amplifier in Spice.
  • Layout generations, LVS, Back annotation
  • Xilinx 8.1
  • Dr. K. Jayakumar, Ph.D.,
  • Ms. S. Saranya, M.E.,
  • Ms. Shabana, M.E.,